In various types of electronic systems, a need exists to sample a digital signal to determine its state, i.e., to determine whether the signal is at a logical “1” or logical “0” level. In practice, such sampling occurs periodically, typically in response to a periodic sample clock pulse. Ideally, sampling should occur at a sufficiently high frequency to minimize jitter, generally defined as the period of uncertainty between a change in state of the sampled signal and the next sample clock pulse. In a worst-case scenario, the sampled signal will change states just after the occurrence of a sample clock, so that nearly an entire sample clock interval will elapse before sampling the input signal again.
Increasing the sampling frequency will reduce the period of uncertainty and thus yield improved jitter performance. However, increasing the sampling frequency will yield more samples. In some electronic systems, bandwidth constraints limit the number of samples capable of being transmitted within a given interval. In such systems, limited opportunities exist for jitter performance improvement.
Thus, there is need for a technique tat achieves increased jitter performance in bandwidth-limited systems.